1. Field of Invention
The present invention relates to a charge pump circuit for a memory device, more particularly to a circuit charging cell capacitors or bitlines up to a full level of power supply voltage, by means of compensating for the loss caused by the threshold voltages of memory transistors with elevated potential higher than the power supply voltage.
2. Description of Background Art
A charge pump circuit is one of a power supply circuit providing an elevated potential VPP higher than the power supply voltage VDD. It is not expected in general that a circuit may produce an output voltage higher than the power supply voltage VDD. However, a semiconductor integrated circuit quite often requires an output voltage higher than the power supply voltage VDD. Especially in memory devices such as a DRAM, more often used is the elevated potential that is higher than the power supply voltage VDD, for the purpose of making up for the loss caused by the threshold voltage of cell transistors.
The usage of the elevated potential is as follows, more specifically.
A wordline driver circuit of a DRAM increases the wordline voltage up to a high voltage of the elevated potential VPP, and then a data voltage VDD of high level on the bitline is written in the cell if the loss is caused by the threshold voltage VT of the NMOS cell transistors. Moreover, the sufficient data voltage is carried to the bitline in reading.
A bitline isolation is achieved in the bitline isolation circuit of a DRAM wherein a full VDD voltage can be transmitted to the memory cell without the loss due to threshold voltage by means of having the gate voltage of the transistors reach a sufficient high voltage. A flip-flop sense amplifier amplifies the data written from a data bus line into VDD and 0 Volt, transmitting the voltages to the cell without the loss of the threshold voltage VT.
In a data output buffer circuit, the driving capability of the load of the output transistor decreases as the power supply voltage is lowered from 5 to 3.3 Volts. A NMOS circuit is used instead of a CMOS circuit since latch-up is likely to happen in the output transistor due to a large current, thereby causing a low charging speed of the load due to the loss of the threshold voltage VT and an insufficient high level of the output voltage VOH. Accordingly, the load is driven to the sufficient high level of the output voltage VOH with high speed by means of elevating the gate voltage of the NMOS circuit up to VPP.
In the above-explained circuit, the magnitude of a high voltage pulse, i.e. the elevated potential VPP, should be bigger than the added value of (VDD+VT), and especially in the wordline driver, a voltage higher than the elevated potential VPP is required since the threshold voltage of the memory cell transistor is higher than other kinds of transistors. The memory cell transistor has the smallest size among other transistors formed on a chip. The threshold voltage VT of a general NMOS transistor is 0.7 to 0.8 Volt, whereas that of the memory cell transistor amounts to about 1.5 Volt. Thus, the wordline driver should be elevated over the maximum value of the threshold voltage VT. The elevated potential VPP, having the threshold voltage VT of the memory cell transistor as a reference, is available for both bitline isolation and data output buffer.
FIG. 1 shows a conventional charge pump circuit for generating an elevated potential VPP.
Referring to FIG. 1, the charge pump circuit generating the elevated potential has a level monitor 6 controlling an oscillator 1 by means of detecting a level of the output elevated potential VPP.
Once an oscillating enable signal OSCEN is generated from a level monitor 6, the oscillator 1 starts to operate, producing a pulse signal OSC. The voltage of node N becomes 2 VDD in the interval of high level of the pulse signal OSC wherein the node has been supplied with the voltage of VDD by the clamp 3 as soon as the NMOS capacitor 2 has been charged. The NMOS transistor 4 is turned on by the node N voltage of 2 VDD and then, the electric charge having been stored in the node N through the turned-on NMOS transistor 4 is supplied to the output terminal and accumulated in the output capacitor 5. The elevated potential VPP has a value higher than or equal to power supply voltage VDD after the electric charges have been supplied to the output capacitor 5 sufficiently with the repeated accumulating operations as is explained above.
However, the quantity of the electric charges supplied by the pulse signal OSC of a single period are fixed to a constant amount when the elevated voltage VPP is generated through the conventional charge pump circuit.
Accordingly, more that one pulse signals are required for supplying sufficient electric charges.
Moreover, the elevated potential becomes higher than is necessary owing to the fixed quantity of the charges in case that the required quantity is less than the quantity supplied on a single period of the pulse signal OSC.